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IV. The INSTRUCTION SET

This section is a quick introduction to the 6809 architecture and insruction set. It is by no means complete. The intention is to familiarize the user who is already proficient at 6800 assembly language programming with the basic structure of 6809 assembly language. For more complete details on the 6809 instruction set you should obtain the proper documentation from the hardware manufacturer.

Programming Model

The 6809 microprocessor has 9 registers that are accessible by the programmer. Four of these are 8-bit registers while the other five are 16-bit registers. Two of the 8-bit registers can, in some instances, be referenced as one 16-bit registers. The registers are as follows:

The 'A' accumulator (A) 8 bit
The 'B' accumulator (B) 8 bit
The Condition Code register (CC) 8 bit
The Direct Page register (DP) 8 bit
The 'X' index register (X) 16 bit
The 'Y' index register (Y) 16 bit
The User stack pointer (U) 16 bit
The System stack pointer (5) 16 bit
The Program Counter (PC) 16 bit

The A and B accumulators can often be referenced as one 16-bit register represented by a 'D' (for Double-accumulator). In these cases, the A accumulator is the most significant half.

The Addressing Modes

There are several possible addressing modes in the 6809 instruction set. One of the best features of the 6809 is the consistency or regularity built into the instruction set. For the most part, any instruction which addresses memory can use any of the addressing modes available. It is not necessary to remember which instructions can use which addressing modes, etc. The addressing modes and a brief description of each follow.

  1. Inherent
    Inherent addressing refers to those instructions which have no addressing associated with them.
    Example:
    ABX add B accumulator to X

  2. Accumulator
    Accumulator addressing is done in those instructions which can specify the A or B accumulator. In some cases this may be the 16-bit D accumulator.
    Example:
    DECA decrement the A accumulator

  3. Immediate
    In Immediate addressing the byte or bytes following the opcode are the information being addressed. These byte or bytes are specified as part of the instruction.
    Example:
    LDA #8 load immediate value (8) into A

  4. Relative - Long and Short
    In Relative addressing, the value of the byte(s) immediately following the opcode (1 if short, 2 if long) are added as a two's complement number to the current value of the program counter (PC register) to produce a new PC location. In the source code, the programmer specifies the desired address to which execution should be transferred and the assembler determines the correct offset to place after the opcode.
    Example:
    LBRA THERE the program will branch to THERE

  5. Extended
    In Extended addressing, the two bytes (16-bits) following the opcode are used as an absolute memory address value.
    Example:
    LDA $1000 load A from memory location 1000 hex

  6. Direct
    In Direct addressing, the single byte (8-bits) following the opcode is used as a pointer into a 256-byte window or "page" of memory. The page used for this purpose is the one currently found in the Direct Page register. Thus, the effective address is a concatenation of the Direct Page register as the most significant half and the byte following the opcode as the least significant half.
    Example:
    LDA $22 load A from memory location $XX22 where XX represents the contents of the DP register

  7. Extended Indirect
    In Extended Indirect addressing, the 16-bit value following the opcode is used to point to two bytes in memory which are used as the effective address.
    Example:
    LDA [$A012] loads A from the address stored at locations $A012 and $A013

  8. Indexed
    The Indexed addressing mode of the 6809 is an extremely powerful method of specifying addresses which is, in general, some sort of offset from the value stored in one of the registers X, Y, U, S, or PC. There are several forms of indexed addressing which could each be considered an addressing mode in itself. We will, however, discuss each as a subset of Indexed addressing in general. Note that except for the Auto-increment and Auto-decrement modes, determining the effective address has no effect on the register being used as the index.

    1. Constant-Offset Indexed
      This mode uses a two's complement offset value found in the byte or bytes following the opcode. The offset is added to the contents of the specified register to produce a 16-bit effective address. The offset may be represented as a number, a symbol, or any valid expression. It can be either positive or negative and can be a full 16-bits.
      Example:
      LDA 0,X loads A from location pointed to by X
      LDA 5216,Y loads A from (Y) plus 5216
      LDA -36,U loads A from (U) minus 36
      LDA VAL,S loads A from (S) plus VAL

    2. Accumulator Indexed
      In Accumulator indexing, the contents of the specified accumulator (A, B, or D) are added to the specified indexing register as a two's complement value. The result is the effective address.
      Example:
      LDA B,Y loads A from (B)+(Y)
      LDX D,S loads X from (D)+(S)

    3. Auto-Increment
      The contents of the selected register are used as the effective address with no offset permitted. After that effective address has been determined, the selected register is incremented by one (for single plus sign) or two (double plus sign).
      Example:
      LDA 0,X+ loads A from X then bumps X by 1
      LDD ,Y++ loads D from Y then bumps Y by 2

    4. Auto-Decrement
      In auto-decrementing, the selected register is first decremented by one (single minus sign) or two (double minus sign). The resulting value, with no offset, is used as the effective address.
      Example:
      LDA 0,-U decrements U by 1 then loads A from address in U
      LDU ,--S decrements S by 2 then loads U from address in S

FURTHER ADDRESSING MODES

Indexed Indirect Addressing

All the Indexed Addressing modes above can also be used in an indirect fashion by enclosing the operand in square brackets. When this is done, the effective address as described in all the above modes is no longer the final effective address. Instead, the two bytes pointed to by that address are used as the effective address.

Examples:
LDA [,X] loads A from the address pointed to by X
LDX [D,U] loads X from the address pointed to by (U)+(D)

If auto-increment or auto-decrement addressing is done in an indirect fashion, they must be a double increment (two plus signs) or double decrement (two minus signs).

PC Relative Addressing

Indexing may be done from the PC register just as from the X, Y, U, or S. The general use of indexing from the PC register is to address some value in a position-independent manner. Thus if we address some value at the current PC plus 10, no matter where the program executes the value will always be addressed. The programmer does not usually know what that constant offset should be, he knows the address of the value he wants to access as an absolute value for the program as assembled. Thus a mechanism has been included in the assembler to automatically determine the offset from the current PC to that absolute address. This mechanism is called PC Relative Addressing. The value specified in a PC Relative address operand is the absolute value. The assembler takes the difference between this absolute value and the current PC and generates that offset as part of the assembled code for the instruction. PC Relative Addressing is distinguished from normal PC Offset Indexing by the use of 'PCR' as the register name instead of 'PC'.

Example:
LEAX STRING,PCR
this instruction determines the offset between the PC and STRING and uses it as an offset for the PC register to determine the effective address

FORCING DIRECT OR EXTENDED ADDRESSING

The 6809 assembler has a mechanism for forcing the assembler to perform either direct or extended addressing. Under normal conditions, the assembler will use direct addressing when possible. To force the assembler to use extended addressing no matter what the conditions, simply precede the operand with a greater than sign ('>'). For example, suppose the DP register was set to $00 (this is the default on reset of the cpu), and that we have a label, BUFPNT, which is at memory location $0010. Normally the instruction:

LDX BUFPNT

would be assembled with direct addressing. If we wished to force extended addressing we could simply enter:

LDX >BUFPNT

and the assembler would use extended addressing.

The same capability exists for forcing direct addressing by preceding the operand with a less than sign ('<'). For example:

LDX <BUFPNT

would force direct addressing. Note that in both cases the greater than or less than sign must be the first character in the operand.

THE ASSEMBLER INSTRUCTION SET

This section contains a brief listing of all the mnemonics accepted by the 6809 assembler. They are listed in four sections, standard 6809 with alternate 6800, 6800 mnemonics not found in 6809, 6801 mnemonics, and non-standard convenience mnemonics. Before the listing, we must setup some notational conventions:

(P)Operand containing immediate, extended, direct, or indexed addressing.
(Q) Operand containing extended, direct, or indexed addressing.
(T) Operand containing indexed addressing only.
R Any register specification: A, B, X, Y, U, S, PC, CC, DP, or D.
dd 8 bit data value
dddd 16 bit data value

6809 MNEMONICS WITH 6800 ALTERNATES

ABX Add B into X
SOURCE FORM: ABX

ADC Add with carry into register

SOURCE FORM: ADCA (P); ADCB (P)
6800 ALTERNATES: ADC A (P); ADC B (P)

ADD Add into register

SOURCE FORM: ADDA (P); ADDB (P); ADDD (P)
6800 ALTERNATES: ADD A (P); ADD B (P)

AND Logical 'AND' into register

SOURCE FORM: ANDA (P); ANDB (P)
6800 ALTERNATES: AND A (P); AND B (P)

ANDCC Logical 'AND' immediate into CC

SOURCE FORM: ANDCC #dd

ASL Arithmetic shift left

SOURCE FORM: ASLA; ASLB; ASL (Q)
6800 ALTERNATES: ASL A; ASL B

ASR Arithmetic shift right

SOURCE FORM: ASRA; ASRB; ASR (Q)
6800 ALTERNATES: ASR A; ASR B

BCC, LBCC Branch (short or long) if carry clear

SOURCE FORM: BCC dd; LBCC dddd

BCS, LBCS Branch (short or long) if carry set

SOURCE FORM: BCS dd; LBCS dddd

BEQ, LBEQ Branch (short or long) if equal

SOURCE FORM: BEQ dd; LBEQ dddd

BGE, LBGE Branch (short or long) if greater than or equal

SOURCE FORM: BGE dd; LBGE dddd

BGT, LBGT Branch (short or long) if greater than

SOURCE FORM: BGT dd; LBGT dddd

BHI, LBHI Branch (short or long) if higher

SOURCE FORM: BHI dd; LBHI dddd

BHS, LBHS Branch (short or long) if higher or same

SOURCE FORM: BHS dd; LBHS dddd

BIT Bit test

SOURCE FORM: BITA (P); BITB (P)
6800 ALTERNATES: BIT A (P); BIT B (P)

BLE, LBLE Branch (short or long) if less than or equal to

SOURCE FORM: BLE dd; LBLE dddd

BLO, LBLO Branch (short or long) if lower

SOURCE FORM: BLO dd; LBLO dddd

BLS, LBLS Branch (short or long) if lower or same

SOURCE FORM: BLS dd; LBLS dddd

BLT, LBLT Branch (short or long) if less than

SOURCE FORM: BLT dd; LBLT dddd

BMI, LBMI Branch (short or long) if minus

SOURCE FORM: BMI dd; LBMI dddd

BNE, LBNE Branch (short or long) if not equal

SOURCE FORM: BNE dd; LBNE dddd

BPL, LBPL Branch (short or long) if plus

SOURCE FORM: BPL dd; LBPL dddd

BRA, LBRA Branch (short or long) always

SOURCE FORM: BRA dd; LBRA dddd

BRN, LBRN Branch (short or long) never

SOURCE FORM: BRN dd; LBRN dddd

BSR, LBSR Branch (short or long) to subroutine

SOURCE FORM: BSR dd; LBSR dddd

BVC, LBVC Branch (short or long) if overflow clear

SOURCE FORM: BVC dd; LBVC dddd

BVS, LBVS Branch (short or long) if overflow set

SOURCE FORM: BVS dd; LBVS dddd

CLR Clear

SOURCE FORM: CLRA; CLRB; CLR (Q)
6800 ALTERNATES: CLR A; CLR B

CMP Compare

SOURCE FORM: CMPA (P); CMPB (P); CMPD (P); CMPX (P); CMPY (P); CMPU (P); CMPS (P)
6800 ALTERNATES: CMP A (P); CMP B (P); CPX (P)

COM Complement (One's complement)

SOURCE FORM: COMA; COMB; COM (Q)
6800 ALTERNATES: COM A; COM B

CWAI Clear and wait for interrupt

SOURCE FORM: CWAI #dd

DAA Decimal adjust accumulator A

SOURCE FORM: DAA

DEC Decrement

SOURCE FORM: DECA, DECB, DEC (Q)
6800 ALTERNATES: DEC A; DEC B

EOR Exclusive 'OR'

SOURCE FORM: EORA (P); EORB (P)
6800 ALTERNATES: EOR A (P); EOR B (P)

EXG Exchange registers

SOURCE FORM: EXG Rl,R2

INC Increment

SOURCE FORM: INCA, INCB, INC (Q)
6800 ALTERNATES: INC A; INC B

JMP Jump to address

SOURCE FORM: JMP dddd

JSR Jump to subroutine at address

SOURCE FORM: JSR dddd

LD Load register from memory

SOURCE FORM: LDA (P); LDB (P); LDD (P); LDX (P); LDY (P); LDU (P); LDS (P)
6800 ALTERNATES: LDAA (P); LDAB (P); LDA A (P); LDA B (P)

LEA Load effective address

SOURCE FORM: LEAX (T); LEAY (T); LEAU (T); LEAS (T)

LSL Logical shift left

SOURCE FORM: LSLA; LSLB; LSL (Q)

LSR Logical shift right

SOURCE FORM: LSRA; LSRB; LSR (Q)
6800 ALTERNATES: LSR A; LSR B

MUL Multiply accumulators

SOURCE FORM: MUL

NEG Negate (Two's complement)

SOURCE FORM: NEGA; NEGB; NEG (Q)
6800 ALTERNATES: NEG A; NEG B

NOP No operation

SOURCE FORM: NOP

OR Inclusive 'OR' into register

SOURCE FORM: ORA (P); ORB (P)
6800 ALTERNATES: ORAA (P); ORAB (P); ORA A (P); ORA B (P)

ORCC Inclusive 'OR' immediate into CC

SOURCE FORM: ORCC #dd

PSHS Push registers onto system stack

SOURCE FORM: PSHS (register list); PSHS #dd
6800 ALTERNATES: PSRA; PSHB; PSH A; PSH B

PSHU Push registers onto user stack

SOURCE FORM: PSHU (register list); PSHU #dd

PULS Pull registers from system stack

SOURCE FORM: PULS (register list); PULS #dd
6800 ALTERNATES: PULA; PULB; PUL A; PUL B

PULU Pull registers from user stack

SOURCE FORM: PULU (register list); PULU #dd

ROL Rotate left

SOURCE FORM: ROLA; ROLB; ROL (Q)
6800 ALTERNATES: ROL A; ROL B

ROR Rotate right

SOURCE FORM: RORA; RORB; ROR (Q)
6800 ALTERNATES: ROR A; ROR B

RTI Return from interrupt

SOURCE FORM: RTI

RTS Return from subroutine

SOURCE FORM: RTS

SBC Subtract with borrow

SOURCE FORM: SBCA (P); SBCB (P);
6800 ALTERNATES: SBC A (P); SBC B (P)

SEX Sign extend

SOURCE FORM: SEX

ST Store register into memory

SOURCE FORM: STA (P); STB (P); STD (P); STX (P); STY (P); STU (P); STS (P)
6800 ALTERNATES: STAA (P); STAB (P); STA A (P); STA B (P)

SUB Subtract from register

SOURCE FORM: SUBA (P); SUBB (P); SUBD (P)
6800 ALTERNATES: SUB A (P); SUB B, (P)

SWI Software interrupt

SOURCE FORM: SWI

SWI2 Software interrupt 2

SOURCE FORM: SWI2

SWI3 Software interrupt 3

SOURCE FORM: SWI3

SYNC Synchronize to interrupt

SOURCE FORM: SYNC

TFR Transfer register to register

SOURCE FORM: TFR Rl,R2

TST Test

SOURCE FORM: TSTA; TSTB; TST (Q)
6800 ALTERNATES: TST A; TST B

SIMULATED 6800 INSTRUCTIONS

ABA Add B to A

CBA Compare B to A

CLC Clear carry bit

CLI Clear interrupt mask

CLV Clear overflow bit

DES Decrement stack pointer

DEX Decrement X

INS Increment stack pointer

INX Increment X

SBA Subtract B from A

SEC Set carry bit

SEI Set interrupt mask

SEV Set overflow bit

TAB Transfer A to B

TAP Transfer A to CC

TBA Transfer B to A

TPA Transfer CC to A

TSX Transfer S to X

TXS Transfer X to S

WAI Wait for interrupt

SIMULATED 6801 MNEMONICS ASLD Arithmetic shift left D

LSRD Logical shift right D

PSHX Push the X register

PULX Pull the X register

LDAD Load accumulator D from memory

STAD Store accumulator D into memory

CONVENIENCE MNEMONICS

BEC,LBEC Branch (short or long) if error clear

BES,LBES Branch (short or long) if error set

CLF Clear FIRQ interrupt mask

CLZ Clear zero condition code bit

SEF Set FIRQ interrupt mask

SEZ Set zero condition code bit

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